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Mono CODEC with Speaker Driver
DESCRIPTION
The WM8974 is a low power, high quality mono CODEC designed for portable applications such as Digital Still Camera or Digital Voice Recorder. The device integrates support for a differential or single ended mic, and includes drivers for speakers or headphone, and mono line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48ks/s. Additional digital filtering options are available in the ADC path, to cater for application filtering such as `wind noise reduction', plus an advanced mixed signal ALC function with noise gate is provided. The digital audio interface supports A-law and -law companding. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8974 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. The speaker and mono outputs use a separate supply of up to 5V which enables increased output power if required. Different sections of the chip can also be powered down under software control by way of the selectable two or three wire control interface. WM8974 is supplied in a very small 4x4mm QFN package, offering high levels of functionality in minimum board area, with high thermal performance.
WM8974
FEATURES
* * * * * * * * * Mono CODEC: Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz DAC SNR 98dB, THD -84dB (`A'-weighted @ 8 - 48ks/s) ADC SNR 94dB, THD -83dB (`A'-weighted @ 8 - 48ks/s) On-chip Headphone/Speaker Driver with `cap-less' connect - 40mW output power into 16 / 3.3V SPKVDD - BTL speaker drive 0.9W into 8 / 5V SPKVDD Additional MONO Line output Multiple analog or `Aux' inputs, plus analog bypass path Mic Preamps: Differential or single end Microphone Interface - Programmable preamp gain - Psuedo differential inputs with common mode rejection - Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for electret microphones
*
OTHER FEATURES * 5 band EQ (record or playback path) * Digital Playback Limiter * Programmable ADC High Pass Filter (wind noise reduction) * Programmable ADC Notch Filter * On-chip PLL * Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) - power consumption <10mA all-on 48ks/s mode * 4x4x0.9mm 24 lead QFN package
APPLICATIONS
* * * * Digital Still Camera Audio Codec Wireless VoIP and other communication device handsets / headsets Portable audio recorder General Purpose low power audio CODEC
WOLFSON MICROELECTRONICS plc
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Production Data, Rev 4.2 March 2007
Copyright (c)2007 Wolfson Microelectronics plc
WM8974 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 8
SIGNAL TIMING REQUIREMENTS .......................................................................9
SYSTEM CLOCK TIMING ............................................................................................. 9 AUDIO INTERFACE TIMING - MASTER MODE .......................................................... 9 AUDIO INTERFACE TIMING - SLAVE MODE............................................................ 10 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 11 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 12
DEVICE DESCRIPTION.......................................................................................13
INTRODUCTION ......................................................................................................... 13 INPUT SIGNAL PATH ................................................................................................. 14 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 19 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 23 OUTPUT SIGNAL PATH ............................................................................................. 35 ANALOGUE OUTPUTS............................................................................................... 42 OUTPUT SWITCH ...................................................................................................... 47 DIGITAL AUDIO INTERFACES................................................................................... 49 AUDIO SAMPLE RATES ............................................................................................. 54 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 55 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 57 CONTROL INTERFACE.............................................................................................. 57
RESETTING THE CHIP........................................................................................58
POWER SUPPLIES .................................................................................................... 58 POWER MANAGEMENT ............................................................................................ 63
REGISTER MAP...................................................................................................65
REGISTER BITS BY ADDRESS ................................................................................. 66
DIGITAL FILTER CHARACTERISTICS ...............................................................77
TERMINOLOGY .......................................................................................................... 77 DAC FILTER RESPONSES......................................................................................... 78 ADC FILTER RESPONSES......................................................................................... 78 DE-EMPHASIS FILTER RESPONSES........................................................................ 79 HIGHPASS FILTER..................................................................................................... 80 5-BAND EQUALISER .................................................................................................. 81
APPLICATIONS INFORMATION .........................................................................85
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 85
PACKAGE DIAGRAM ..........................................................................................86 IMPORTANT NOTICE ..........................................................................................87
ADDRESS: .................................................................................................................. 87
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WM8974
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE WM8974GEFL/V WM8974GEFL/RV Note: Reel Quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 24-lead QFN (4x4x0.9mm) (Pb-free) 24-lead QFN (4x4x0.9mm) (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PACKAGE BODY TEMPERATURE 260oC 260oC
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WM8974 PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME MICBIAS AVDD AGND DCVDD DBVDD DGND ADCDAT DACDAT FRAME BCLK MCLK CSB/GPIO SCLK SDIN MODE MONOOUT SPKOUTP SPKGND SPKOUTN SPKVDD AUX VMID MICN MICP Supply Supply Supply Supply Supply Digital Output Digital Input Digital Input / Output Digital Input / Output Digital Input Digital Input / Output Digital Input Digital Input / Output Digital Input Analogue Output Analogue Output Supply Analogue Output Supply Analogue Input Reference Analogue Input Analogue Input TYPE Analogue Output Microphone bias Analogue supply (feeds ADC and DAC) Analogue ground (feeds ADC and DAC) Digital core supply Digital buffer (input/output) supply Digital ground ADC digital audio data output DAC digital audio data input DAC and ADC sample rate clock or frame synch Digital audio port clock Master clock input DESCRIPTION
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3-Wire MPU chip select or general purpose input/output pin. 3-Wire MPU clock Input / 2-Wire MPU Clock Input 3-Wire MPU data Input / 2-Wire MPU Data Input Control interface mode selection pin. Mono output Speaker output positive Speaker ground (feeds speaker and mono output amps only) Speaker output Negative Speaker supply (feeds speaker and mono output amps only) Auxiliary analogue input Decoupling for midrail reference voltage Microphone negative input Microphone positive input (common mode)
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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WM8974
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD supply voltages SPKVDD supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Notes 1. 2. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. MIN -0.3V -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +4.2 +7V DVDD +0.3V AVDD +0.3V +85C +150C
30C max / 85% RH max
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Speaker supply Ground Notes 1. 2. 3. 4. 5. When using PLL, DCVDD must be 1.9V or higher. AVDD must be DCVDD. DBVDD must be DCVDD. In non-boosted mode, SPKVDD must be AVDD, if boosted SPKVDD must be 1.5x AVDD. When using PLL, DCVDD must be 1.9V. SYMBOL DCVDD DBVDD AVDD SPKVDD DGND,AGND,SPKGND TEST CONDITIONS MIN 1.71 1.71 2.5 2.5 0 TYP MAX 3.6 3.6 3.6 5.5 UNIT V V V V V
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WM8974 ELECTRICAL CHARACTERISTICS
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Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Microphone Inputs (MICN, MICP) Full-scale Input Signal Level (Note 1) - note this changes with AVDD Mic PGA equivalent input noise Input resistance Input resistance Input resistance Input resistance Input resistance Input Capacitance Programmable Gain Programmable Gain Step Size Mute Attenuation Selectable Input Gain Boost (0/+20dB) Gain Boost Automatic Level Control (ALC)/Limiter - ADC only Target Record Level Programmable Gain Programmable Gain Step Size Gain Hold Time (Note 2) Gain Ramp-Up (Decay) Time (Note 3) tHOLD tDCY Guaranteed Monotonic MCLK=12.288MHz (Note 4) ALCMODE=0 (ALC), MCLK=12.288MHz (Note 4) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 4) Gain Ramp-Down (Attack) Time (Note 3) tATK ALCMODE=0 (ALC), MCLK=12.288MHz (Note 4) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 4) Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 5) Total Harmonic Distortion (Note 6) Auxilliary Analogue Input (AUX) Full-scale Input Signal Level (0dB) - note this changes with AVDD Input Resistance Input Capacitance VINFS RAUXIN CAUXIN AUXMODE=0 1.0 0 20 10 Vrms dBV k pF SNR THD A-weighted, 0dB PGA gain -1dBFS input, 0dB PGA gain 85 -75 94 -83 dB dB -28.5 -12 0.75 0, 2.67, 5.33, 10.67, ... , 43691 (time doubles with each step) 3.3, 6.6, 13.1, ... , 3360 (time doubles with each step) 0.73, 1.45, 2.91, ... , 744 (time doubles with each step) 0.83, 1.66, 3.33, ... , 852 (time doubles with each step) 0.18, 0.36, 0.73, ... , 186 (time doubles with each step) ms -6 35.25 dB dB dB ms ms 0 20 dB Guaranteed monotonic VINFS PGABOOST = 0dB INPPGAVOL = 0dB 1.0 0 150 Gain set to 35.25dB Gain set to 0dB Gain set to -12dB MICP2INPPGA = 1 MICP2INPPGA = 0 1.6 47 75 94 94 10 -12 0.75 108 35.25 Vrms dBV uV k k k k k pF dB dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
At 35.25dB gain RMICIN RMICIN RMICIN RMICIP RMICIP CMICIN
MIC Input Programmable Gain Amplifier (PGA)
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WM8974
Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Signal to Noise Ratio (Note 5) Total Harmonic Distortion + Noise (Note 6) 0dB Full Scale output voltage (Note 9) SYMBOL SNR THD+N TEST CONDITIONS A-weighted RL = 10 k full-scale signal MONOBOOST=0 MONOBOOST=1 Speaker Output PGA Programmable Gain Programmable Gain Step Size Output Power Total Harmonic Distortion + Noise (Note 6) PO THD+N Guaranteed monotonic BTL Speaker Output (SPKOUTP, SPKOUTN with 8 bridge tied load) Output power is very closely correlated with THD; see below PO =180mW, RL = 8, SPKVDD=3.3V PO =400mW, RL = 8, SPKVDD=3.3V PO =360mW, RL = 8, SPKVDD=5V PO =800mW, RL = 8, SPKVDD=5V Signal to Noise Ratio SNR SPKVDD=3.3V, RL = 8 SPKVDD=5V, RL = 8 Power Supply Rejection Ratio `Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) Signal to Noise Ratio Total Harmonic Distortion + Noise (Note 6) SNR THD+N Po=20mW, RL = 16, SPKVDD=3.3V Po=20mW, RL = 32, SPKVDD=3.3V Microphone Bias Bias Voltage (MBVSEL=0) Bias Voltage (MBVSEL=1) Bias Current Source Output Noise Voltage Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level VIH VIL VOH VOL IOL=1mA IOH-1mA 0.9xDVDD 0.1xDVDD 0.7xDVDD 0.3xDVDD V V V V VMICBIAS VMICBIAS IMICBIAS Vn 1K to 20kHz 15 0.9*AVDD 0.65*AVDD 3 V V mA nV/Hz 100 0.02 -74 0.017 - 75 dB % dB % dB 90 0.03 -70 5.0 -26 0.02 -75 0.06 -65 101 102 50 % dB % dB % dB % dB dB dB dB -57 1 6 dB dB MIN 90 TYP 98 -84 AVDD/3.3 1.5x (AVDD/3.3) MAX UNIT dB dB VRMS
Digital to Analogue Converter (DAC) to MONO output (all data measured with 10k / 50pF load)
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WM8974
TERMINOLOGY
1. 2. 3. 4. 5. 6. 7.
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MICN input only in single ended microphone configuration. Maximum input signal to MICP without distortion is -3dBV. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to change it's gain by 6dB. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. The maximum output voltage can be limited by the speaker power supply. If MONOBOOST=1 then SPKVDD should be 1.5xAVDD or higher to prevent clipping taking place in the output stage.
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WM8974
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz. TMCLKY TMCLKDS MCLK=SYSCLK (=256fs) MCLK input to PLL Note 1 81.38 20 60:40 40:60 ns ns SYMBOL CONDITIONS MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
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WM8974
Test Conditions
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DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge Note: BCLK period should always be greater than MCLK period. tDL tDDA tDST tDHT 10 10 10 10 ns ns ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low FRAME set-up time to BCLK rising edge FRAME hold time from BCLK rising edge DACDAT hold time from BCLK rising edge DACDAT set-up time to BCLK rising edge ADCDAT propagation delay from BCLK falling edge tBCY tBCH tBCL tLRSU tLRH tDH tDS tDD 160 64 64 10 10 10 10 20 ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8974
CONTROL INTERFACE TIMING - 3-WIRE MODE
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8974
CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t5 t3
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t8
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8974
DEVICE DESCRIPTION
INTRODUCTION
The WM8974 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras with mono audio, record and playback capability, voice recorders, wireless VoIP headsets and games console accessories.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Two microphone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. These inputs have a user programmable gain range of -12dB to +35.25dB using internal resistors. After the input PGA stage comes a boost stage which can add a further 20dB of gain. A microphone bias is output from the chip which can be used to bias the microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
AUX INPUT
The device includes a mono input, AUX, that can be used as an input for warning tones (beep) etc. The output from this circuit can be summed into the mono output and/or the speaker output paths, so allowing for mixing of audio with `backing music' etc as required. This path can also be summed into the input in a flexible fashion, either to the input PGA as a second microphone input or as a line input. The configuration of this circuit, with integrated on-chip resistors allows several analogue signals to be summed into the single AUX input if required. ADC The mono ADC uses a multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used in voice dictation, up to the 48ks/s rate used in high quality audio applications.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable mono audio type applications.
DIGITAL FILTERING
Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8ks/s to 48ks/s. Application specific digital filters are also available which help to reduce the effect of specific noise sources such as `wind noise'. The filters include a programmable ADC high pass filter, a programmable ADC notch filter and a 5-band equaliser that can be applied to either the ADC or the DAC path in order to improve the overall audio sound from the device.
OUTPUT MIXING AND VOLUME ADJUST
Flexible mixing is provided on the outputs of the device; a mixer is provided for the speaker outputs, and an additional mono summer for the mono output. These mixers allow the output of the DAC, the output of the ADC volume control and the Auxilliary input to be combined. The output volume can be adjusted using the integrated digital volume control and there is additional analogue gain adjustment capability on the speaker output.
AUDIO INTERFACES
The WM8974 has a standard audio interface, to support the transmission of audio data to and from the chip. This interface is a 4 wire standard audio interface which supports a number of audio data formats including I2S, DSP Mode, MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes.
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WM8974
CONTROL INTERFACES
Production Data To allow full software control over all its features, the WM8974 offers a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if MODE is low then 2-wire control mode is selected. In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8974 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC/ADC. However, a PLL is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the CSB/GPIO pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8974 has given much attention to power consumption without compromising performance. It operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control, includes standby and power off modes.
INPUT SIGNAL PATH
The WM8974 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA block which then feeds into a gain boost/mixer stage.
MICROPHONE INPUTS
The WM8974 can accommodate a variety of microphone configurations including single ended and differential inputs. The inputs through the MICN, MICP and optionally AUX pins are amplified through the input PGA as shown in Figure 6 . A pseudo differential input is the preferential configuration where the positive terminal of the input PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when AUX2INPPGA=1) input pins. Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting MICP2INPPGA to 0. In differential mode the larger signal should be input to MICP and the smaller (e.g. noisy ground connection) should be input to MICN.
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WM8974
Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input)
REGISTER ADDRESS R44 Input Control
BIT 0
LABEL MICP2INPPGA 1
DEFAULT
DESCRIPTION Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal.
1
MICN2INPPGA
1
2
AUX2INPPGA
0
The input PGA is enabled by the IPPGAEN register bit. REGISTER ADDRESS R2 Power Management 2 2 BIT LABEL INPPGAEN DEFAULT 0 DESCRIPTION Input microphone PGA enable 0 = disabled 1 = enabled
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INPUT PGA VOLUME CONTROL
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The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the MICP pin when MICP2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled automatically and the INPPGAVOL bits should not be used. REGISTER ADDRESS BIT LABEL INPPGAVOL DEFAULT 010000 DESCRIPTION Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain)
R45 5:0 Input PGA volume control
6
INPPGAMUTE
0
7
INPPGAZC
0
R32 ALC control 1
8
ALCSEL
0
Table 1 Input PGA Volume Control
AUXILLIARY INPUT
An auxilliary input circuit (Figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. The circuit is enabled by the register bit AUXEN.
Figure 7 Auxiliary Input Circuit The AUXMODE register bit controls the auxiliary input mode of operation: In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the AUX pin will be buffered and inverted through the aux circuit using only the internal components.
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WM8974
In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. When used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20k resistors relative to the higher tolerance external resistors. REGISTER ADDRESS R1 Power management 1 R44 Input control 6 BIT LABEL AUXEN DEFAULT 0 DESCRIPTION Auxiliary input buffer enable 0 = OFF 1 = ON 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed)
3
AUXMODE
0
Table 2 Auxiliary Input Buffer Control
INPUT BOOST
The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the MICP input pin (when not using a differential microphone configuration). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 8.
Figure 8 Input Boost Stage The input PGA path can have a +20dB boost (PGABOOST=1) a 0dB pass through (PGABOOST=0) or be completely isolated from the input boost circuit (INPPGAMUTE=1). REGISTER ADDRESS R45 Input PGA gain control R47 Input BOOST control 6 BIT LABEL INPPGAMUTE DEFAULT 0 DESCRIPTION Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
8
PGABOOST
0
Table 3 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register bits. When AUX2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. PD Rev 4.2 March 2007 17
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Production Data The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. REGISTER ADDRESS R47 Input BOOST control BIT 2:0 LABEL AUX2BOOSTVOL DEFAULT 000 DESCRIPTION Controls the auxiliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage
6:4
MICP2BOOSTVOL
000
Table 4 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 BIT 4 LABEL BOOSTEN DEFAULT 0 DESCRIPTION Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON
Table 5 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS R1 Power management 1 4 BIT LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 6 Microphone Bias Enable
REGISTER ADDRESS R44 Input Control 8
BIT
LABEL MBVSEL
DEFAULT 0
DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD
Table 7 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
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MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD MBVSEL=1 MICBIAS = 1.3 x VMID = 0.65 X AVDD
VMID internal resistor internal resistor
MB
AGND
Figure 9 Microphone Bias Schematic
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM8974 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in .
Figure 10 ADC Digital Filter Path The ADC is enabled by the ADCEN register bit. REGISTER ADDRESS R2 Power management 2 Table 8 ADC Enable 0 BIT LABEL ADCEN DEFAULT 0 DESCRIPTION 0 = ADC disabled 1 = ADC enabled
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Production Data The polarity of the output signal can also be changed under software control using the ADCPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS R14 ADC Control 3 BIT LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC oversample rate select: 0=64x (lower power) 1=128x (best performance) 0=normal 1=inverted
0
ADCPOL
0
Table 9 ADC Oversample Rate Select
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 11. REGISTER ADDRESS R14 ADC Control 8 BIT LABEL HPFEN DEFAULT 1 DESCRIPTION High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 11 for details.
7
HPFAPP
0
6:4 Table 10 ADC Filter Select
HPFCUT
000
HPFCUT SR=101/100 8 000 001 010 011 100 101 110 111 82 102 131 163 204 261 327 408 11.025 113 141 180 225 281 360 450 563 12 122 153 156 245 306 392 490 612 16 82 102 131 163 204 261 327 408
FS (KHZ) SR=011/010 22.05 113 141 180 225 281 360 450 563 24 122 153 156 245 306 392 490 612 32 82 102 131 163 204 261 327 408 SR=001/000 44.1 113 141 180 225 281 360 450 563 48 122 153 156 245 306 392 490 612
Table 11 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 11.
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PROGRAMMABLE NOTCH FILTER
A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup.
REGISTER ADDRESS R27 Notch Filter 1 7
BIT 6:0
LABEL NFA0[13:7] NFEN
DEFAULT 0 0
DESCRIPTION Notch Filter a0 coefficient, bits [13:7] Notch filter enable: 0=Disabled 1=Enabled Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a0 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [13:7] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high.
8
NFU
0
R28 Notch Filter 2
6:0 8
NFA0[6:0] NFU]
0 0
R29 Notch Filter 3
6:0 8
NFA1[13:7] NFU
0 0
R30 Notch Filter 4
6:0 8
NFA1[6:0] NFU
0 0
Table 12 Notch Filter Function The coefficients are calculated as follows:
a0 =
1 - tan( wb / 2) 1 + tan( wb / 2)
a1 = -(1 + a0 ) cos(w0 )
Where:
w0 = 2f c / f s
wb = 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212
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DIGITAL ADC VOLUME CONTROL
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The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: Gain = 0.5 x (x-255) dB for 1 x 255, MUTE for x = 0 REGISTER ADDRESS R15 ADC Digital Volume BIT 7:0 LABEL ADCVOL [7:0] DEFAULT 11111111 ( 0dB ) DESCRIPTION ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 13 ADC Volume
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The WM8974 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (ALCLVL). If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set by ALCATK. The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL.
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
REGISTER ADDRESS R32 (20h) ALC Control 1
BIT 2:0
LABEL ALCMIN [2:0]
DEFAULT 000 (-12dB)
DESCRIPTION Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB
5:3
ALCMAX [2:0]
111 (+35.25dB) Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB 0 ALC function select 0 = ALC disabled 1 = ALC enabled ALC target - sets signal level at ADC input 1111 = -6dBFS 1110 = -7.5dBFS 1101 = -9dBFS 1100 = -10.5dBFS 1011 = -12dBFS 1010 = -13.5dBFS 1001 = -15dBFS 1000 = -16.5dBFS 0111 = -18dBFS 0110 = -19.5dBFS 0101 = -21dBFS 0100 = -22.5dBFS 0011 = -24dBFS 0010 = -25.5dBFS 0001 = -27dBFS 0000 = -28.5dBFS
8
ALCSEL
R33 (21h) ALC Control 2
3:0
ALCLVL [3:0]
1011 (-12dB)
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REGISTER ADDRESS 8 BIT LABEL ALCZC DEFAULT 0 (zero cross off) 0000 (0ms)
Production Data DESCRIPTION ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step 0000 0001 0010 410us 820us 1.64ms Per 6dB 3.38ms 6.56ms 13.1ms 3.36s 90% of range 23.6ms 47.2ms 94.5ms 24.2s
7:4
ALCHLD [3:0]
R34 (22h) ALC Control 3
8
ALCMODE
0
7:4
ALCDCY [3:0]
0011 (26ms/6dB)
... (time doubles with every step) 1010 or 420ms higher 0011 (5.8ms/6dB)
Decay (gain ramp-up) time (ALCMODE ==1) Per step 0000 0001 0010 1010 90.8us 182us 363us 93ms Per 6dB 726us 1.45ms 2.91ms 744ms 90% of range 5.23ms 10.5ms 20.9ms 5.36s
... (time doubles with every step) 3:0 ALCATK [3:0] 0010 (3.3ms/6dB) ALC attack (gain ramp-down) time (ALCMODE == 0) Per step 0000 0001 0010 104us 208us 416us Per 6dB 832us 1.66ms 3.33ms 852ms 90% of range 6ms 12ms 24ms 6.13s
... (time doubles with every step) 1010 or 106ms higher 0010 (726us/6dB)
ALC attack (gain ramp-down) time (ALCMODE == 1) Per step 0000 0001 0010 1010 or higher 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363us 726us 186ms 90% of range 1.31ms 2.62ms 5.23ms 1.34s
... (time doubles with every step)
Table 14 ALC Control Registers
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When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.
NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this.
Figure 11 ALC Normal Mode Operation
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LIMITER MODE
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In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at start-up. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be the gain at switchover. The diagram below shows an example of limiter mode.
Figure 12 ALC Limiter Mode Operation
ATTACK AND DECAY TIMES
The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain range. Note that, these times will vary slightly depending on the sample rate used (specified by the SR register).
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NORMAL MODE
ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATK 104s 208s 416s 832s 1.66ms 3.33ms 6.66ms 13.3ms 26.6ms 53.2ms 106ms Attack Time (s) tATK6dB tATK90% 832s 6ms 1.66ms 12ms 3.33ms 24ms 6.66ms 48ms 13.3ms 96ms 26.6ms 192ms 53.2ms 384ms 106ms 767ms 213.2ms 1.53s 426ms 3.07s 852ms 6.13s
ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCY 410s 820s 1.64ms 3.28ms 6.56ms 13.1ms 26.2ms 52.5ms 105ms 210ms 420ms Decay Time (s) tDCY6dB tDCY90% 3.28ms 23.6ms 6.56ms 47.2ms 13.1ms 94.5ms 26.2ms 189ms 52.5ms 378ms 105ms 756ms 210ms 1.51s 420ms 3.02s 840ms 6.05s 1.68s 12.1s 3.36s 24.2s
Table 15 ALC Normal Mode (Attack and Decay times)
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LIMITER MODE
Production Data
ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tATKLIM 22.7s 45.4S 90.8S 182S 363S 726S 1.45ms 2.9ms 5.81ms 11.6ms 23.2ms Attack Time (s) tATKLIM6dB tATKLIM90% 182s 1.31ms 363s 2.62ms 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s
ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 tDCYLIM 90.8s 182S 363S 726S 1.45ms 2.91ms 5.81ms 11.6ms 23.2ms 46.5ms 93ms Attack Time (s) tDCYLIM6dB tDCYLIM90% 726s 5.23ms 1.45ms 10.5ms 2.91ms 20.9ms 5.81ms 41.8ms 11.6ms 83.7ms 23.2ms 167ms 46.5ms 335ms 93ms 669ms 186ms 1.34s 372ms 2.68s 744ms 5.36s
Table 16 ALC Limiter Mode (Attack and Decay times)
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MINIMUM AND MAXIMUM GAIN
The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.
REGISTER ADDRESS R32 ALC Control 1
BIT 5:3 2:0
LABEL ALCMAX ALCMIN
DEFAULT 111 000
DESCRIPTION Set Maximum Gain of PGA Set minimum gain of PGA
Table 17 ALC Max/Min Gain
In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level. ALCMIN sets the minimum gain value which can be applied to the signal.
Figure 13 ALC Min/Max Gain
ALCMAX 111 110 101 100 011 010 001 000
Maximum Gain (dB) 35.25 29.25 23.25 17.25 11.25 5.25 -0.75 -6.75
Table 18 ALC Max Gain Values
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ALCMIN 000 001 010 011 100 101 110 111 Minimum Gain (dB) -12 -6 0 6 12 18 24 30
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Table 19 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC starting gain is set between the ALCMAX and ALCMIN limits.
ALC HOLD TIME (NORMAL MODE ONLY)
In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase (gain increasing). The hold time is set by the ALCHLD register.
REGISTER ADDRESS R33 ALC Control 2
BIT 7:4
LABEL ALCHLD
DEFAULT 0000
DESCRIPTION ALC hold time before gain is increased.
Table 20 ALC Hold Time If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation.
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Figure 14 ALCLVL
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Figure 15 ALC Hold Time
ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
tHOLD (s) 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s
Table 21 ALC Hold Time Values
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PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE (NORMAL MODE ONLY)
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8974 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS R35 (23h) ALC Noise Gate Control BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db 011 = -57dB 100 = -63dB 101 = -69dB 110 = -75dB 111 = -81dB Noise gate function enable 1 = enable 0 = disable
3
NGATEN
0
Table 22 ALC Noise Gate Control
The diagrams below show the response of the system to the same signal with and without noise gate.
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Figure 16 ALC Operation Above Noise Gate Threshold
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Figure 17 Noise Gate Operation
OUTPUT SIGNAL PATH
The WM8974 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by bit DACEN. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8974, irrespective of whether the DACs are running or not. The WM8974 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser A digital peak limiter. Sigma-Delta Modulation The high performance sigma-delta audio DAC converts the digital data into an analogue signal.
Figure 18 DAC Digital Filter Path
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Production Data The analogue output from the DAC can then be mixed with the AUX analogue input and the ADC analogue input. The mix is fed to the output drivers, SPKOUTP/N, and MONOOUT. MONOOUT: can drive a 16 or 32 headphone or line output or can be a buffered version of VMID (When MONOMUTE=1). SPKOUTP/N: can drive a 16 or 32 stereo headphone or stereo line output, or an 8 BTL mono speaker.
DIGITAL HI-FI DAC VOLUME CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255; REGISTER ADDRESS R11 DAC Digital Volume BIT 7:0 LABEL DACVOL [7:0] MUTE for X = 0 DEFAULT 11111111 ( 0dB ) DESCRIPTION DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 23 DAC Volume
HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC)
After passing through the graphic equaliser filters, digital `de-emphasis' can be applied to the audio data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. REGISTER ADDRESS R10 DAC Control BIT 5:4 LABEL DEEMPH DEFAULT 00 DESCRIPTION De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate
Table 24 De-Emphasis The DAC is enabled by the DACEN register bit. REGISTER ADDRESS R3 Power Management 3 Table 25 DAC Enable The WM8974 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit to zero. 0 BIT LABEL DACEN DEFAULT 0 DESCRIPTION DAC enable 0 = DAC disabled 1 = DAC enabled
REGISTER ADDRESS R10 DAC Control
BIT 6
LABEL DACMU 0
DEFAULT
DESCRIPTION DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled
Table 26 DAC Control Register
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The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters a multi-bit, sigma-delta DAC, which converts it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. The DAC output defaults to non-inverted. Setting DACPOL will invert the DAC output phase.
AUTOMUTE
The DAC has an automute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is release as soon as a non-zero sample is detected. Automute can be disabled using the AMUTE control bit. REGISTER ADDRESS R10 DAC Control BIT 2 LABEL AMUTE 0 DEFAULT DESCRIPTION DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled
Table 27 DAC Auto Mute Control Register
DAC OUTPUT LIMITER
The WM8974 has a digital output limiter function. The operation of this is shown in Figure 19. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
Figure 19 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Table 28, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value.
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VOLUME BOOST
Production Data
The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
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REGISTER ADDRESS R24 DAC digital limiter control 1 BIT 3:0 LABEL LIMATK DEFAULT 0010 DESCRIPTION Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 7:4 LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s 8 LIMEN 0 Enable the DAC digital limiter: 0=disabled 1=enabled Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved 6:4 LIMLVL 000 Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Table 28 DAC Digital Limiter Control
R25 DAC digital limiter control 2
3:0
LIMBOOST
0000
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GRAPHIC EQUALISER
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A 5-band graphic EQ is provided, which can be applied to the ADC or DAC path under control of the EQMODE register bit. REGISTER ADDRESS R18 EQ Control 1 8 BIT LABEL EQMODE 1 DEFAULT DESCRIPTION 0 = Equaliser applied to ADC path 1 = Equaliser applied to DAC path
Table 29 EQ DAC or ADC Path Select The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth. REGISTER ADDRESS R18 EQ Band 1 Control BIT 4:0 6:5 LABEL EQ1G EQ1C DEFAULT 01100 (0dB) 01 DESCRIPTION Band 1 Gain Control. See Table 35 for details. Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz Table 30 EQ Band 1 Control REGISTER ADDRESS R19 EQ Band 2 Control BIT 4:0 6:5 LABEL EQ2G EQ2C DEFAULT 01100 (0dB) 01 DESCRIPTION Band 2 Gain Control. See Table 35 for details. Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz 11=500Hz Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ2BW
0
Table 31 EQ Band 2 Control
REGISTER ADDRESS R20 EQ Band 3 Control
BIT 4:0 6:5
LABEL EQ3G EQ3C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 3 Gain Control. See Table 35 for details. Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ3BW
0
Table 32 EQ Band 3 Control
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REGISTER ADDRESS R21 EQ Band 4 Control BIT 4:0 6:5 LABEL EQ4G EQ4C DEFAULT 01100 (0dB) 01 DESCRIPTION Band 4 Gain Control. See Table 35 for details Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ4BW
0
Table 33 EQ Band 4 Control
REGISTER ADDRESS R22 EQ Band 5 Gain Control
BIT 4:0 6:5
LABEL EQ5G EQ5C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 5 Gain Control. See Table 35 for details. Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz
Table 34 EQ Band 5 Control
GAIN REGISTER 00000 00001 00010 .... (1dB steps) 01100 01101 11000 11001 to 11111 0dB -1dB -12dB Reserved +12dB +11dB +10dB
GAIN
Table 35 Gain Register Table
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ANALOGUE OUTPUTS
Production Data
The WM8974 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1.5V rms signals (equivalent to 3V rms into a bridge tied speaker) as shown in Figure 20.
Figure 20 Speaker and Mono Analogue Outputs The Mono and speaker outputs have output driving stages which can be controlled by the register bits MONOBOOST and SPKBOOST respectively. Each output stage has a selectable gain boost of 1.5x. When this boost is enabled the output DC level is also level shifted (from AVDD/2 to 1.5xAVDD/2) to prevent the signal from clipping. A dedicated amplifier, as shown in Figure 20, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if SPKVDD is not equal to or greater than 1.5xAVDD this boost mode may result in signals clipping. Table 37 summarises the effect of the SPKBOOST/MONOBOOST control bits.
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REGISTER ADDRESS R49 Output control 2 BIT LABEL SPKBOOST DEFAULT 0 DESCRIPTION Speaker output boost stage control (see Table 37 for details) 0=No boost (outputs are inverting buffers) 1 = 1.5x gain boost Mono output boost stage control (see Table 37 for details) 0=No boost (output is inverting buffer) 1=1.5x gain boost Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost)
3
MONOBOOST
0
R1 Power management 1
8
BUFDCOPEN
0
Table 36 Output Boost Control
SPKBOOST/ MONOBOOST 0 1
OUTPUT STAGE GAIN 1x 1.5x
OUTPUT DC LEVEL AVDD/2 1.5xAVDD/2
OUTPUT STAGE CONFIGURATION Inverting Non-inverting
Table 37 Output Boost Stage Details
SPKOUTP/SPKOUTN OUTPUTS
The SPKOUT pins can drive a single bridge tied 8 speaker or two headphone loads of 16 or 32 or a line output (see Headphone Output and Line Output sections, respectively). The signal to be output on SKPKOUT comes from the Speaker Mixer circuit and can be any combination of the DAC output, the Bypass path (output of the boost stage) and the AUX input. The SPKOUTP/N volume is controlled by the SPKVOL register bits. Note that gains over 0dB may cause clipping if the signal is large. The SPKMUTE register bit causes the speaker outputs to be muted (the output DC level is driven out). The output pins remains at the same DC level (VMIDOP), so that no click noise is produced when muting or un-muting. The SPKOUTN pin always drives out an inverted version of the SPKOUTP signal. REGISTER ADDRESS R50 Speaker mixer control 0 BIT LABEL DAC2SPK DEFAULT 1 DESCRIPTION Output of DAC to speaker mixer input 0 = not selected 1 = selected Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB
1
BYP2SPK
0
5
AUX2SPK
0
R40 Bypass path attenuation control
1
SPKATTN
0
Table 38 Speaker Mixer Control
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REGISTER ADDRESS R54 Speaker volume control 7 BIT LABEL SPKZC DEFAULT 0
Production Data
DESCRIPTION Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB ... (1.0 dB steps) 111001=0dB ... 000000=-57dB
6
SPKMUTE
0
5:0
SPKVOL [5:0]
111001 (0dB)
Table 39 SPKOUT Volume Control
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * input clock period.
REGISTER ADDRESS R7 0 Additional control
BIT
LABEL SLOWCLKEN
DEFAULT 0
DESCRIPTION Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled
Table 40 Timeout Clock Enable Control
MONO MIXER AND OUTPUT
The MONOOUT pin can drive a 16 or 32 headphone or a line output or be used as a DC reference for a headphone output (see Headphone Output section). It can be selected to drive out any combination of DAC, Bypass (output of input BOOST stage) and AUX. This output is enabled by setting bit MONOEN.
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WM8974
REGISTER ADDRESS R56 Mono mixer control BIT 0 LABEL DAC2MONO DEFAULT 0 DESCRIPTION Output of DAC to mono mixer input 0 = not selected 1 = selected Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected Output of Auxillary amplifier to mono mixer input: 0 = not selected 1 = selected 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB
1
BYP2MONO
0
2
AUX2MONO
0
6
MONOMUTE
0
R40 Bypass path attenuation control
2
MONOATTN
0
Table 41 Mono Mixer Control
ENABLING THE OUTPUTS
Each analogue output of the WM8974 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8974 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see "Power Management" and "Applications Information" sections).
REGISTER ADDRESS R1 Power management 1 R3 Power management 3 2 8 3 2 3 5 6 7
BIT
LABEL BUFIOEN BUFDCOPEN BIASEN SPKMIXEN MONOMIXEN SPKPEN SPKNEN MONOEN 0 0 0 0 0 0 0 0
DEFAULT
DESCRIPTION Unused input/output tie off buffer enable Output stage 1.5xAVDD/2 driver enable Analogue amplifiers bias enable Speaker Mixer enable Mono mixer enable SPKOUTP enable SPKOUTN enable MONOOUT enable
Note: All "Enable" bits are 1 = ON, 0 = OFF Table 42 Output Stages Power Management Control
UNUSED ANALOGUE INPUTS/OUTPUTS
Whenever an analogue input/output is disabled, it remains connected to a voltage source (either AVDD/2 or 1.5xAVDD/2 as appropriate) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI contol bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30k.
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REGISTER ADDRESS R49 0 BIT LABEL VROI 0 DEFAULT
Production Data
DESCRIPTION VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k
Table 43 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST or MONOBOOST bits are set then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled. Table 44 summarises the tie-off options for the speaker and mono output pins.
Figure 21 Unused Input/Output Pin Tie-off Buffers MONOEN/ SPKN/PEN 0 0 0 0 1 1 MONOBOOST/ SPKBOOST 0 0 1 1 0 1 VROI 0 1 0 1 X X OUTPUT CONFIGURATION 1k tieoff to AVDD/2 30k tieoff to AVDD/2 1k tieoff to 1.5xAVDD/2 30k tieoff to 1.5xAVDD/2 Output enabled (DC level=AVDD/2) Output enabled (DC level=1.5xAVDD/2)
Table 44 Unused Output Pin Tie-off Options
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WM8974
When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. For example when a line is plugged into a jack socket. In this mode, enabled by setting GPIOSEL=001, pin CSB/GPIO switches between mono and speaker outputs (e.g. when pin 12 is connected to a mechanical switch in the headphone socket to detect plug-in). The GPIOPOL bit reverses the polarity of the CSB/GPIO input pin. Note that the speaker outputs and the mono output must be enabled for this function to work (see Table 45). The CSB/GPIO pin has an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This debounce circuit is clocked from a slow clock with period 221 x MCLK, enabled using the SLOWCLKEN register bit.
OUTPUT SWITCH
GPIOPOL
CSB/GPIO
SPKNEN/ SPKPEN X X 0 1 X X 0 1 0 1 X X 0 1 X X
MONOEN
SPEAKER ENABLED No No No Yes No No No Yes
MONO OUTPUT ENABLED No Yes No No No Yes No No
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Table 45 Output Switch Operation (GPIOSEL=001)
THERMAL SHUTDOWN
The speaker outputs can drive very large currents. To protect the WM8974 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125oC. See General Purpose Input/Output section.
REGISTER ADDRESS R49 Output control 1
BIT
LABEL TSDEN 1
DEFAULT
DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 46 Thermal Shutdown
SPEAKER OUTPUT
SPKOUTP/N can differentially drive a mono 8 Bridge Tied Load (BTL) speaker as shown below.
Figure 22 Speaker Output Connection
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HEADPHONE OUTPUT
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The speaker outputs can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Headphone Output using DC Blocking Capacitors: DC Coupled Headphone Output:
Figure 23 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the MONOOUT pin. The MONOOUT pin can be configured as a DC output driver by setting the MONOMUTE register bit. The DC voltage on MONOOUT in this configuration is equal to the DC offset on the SPROUTP and SPKOUTN pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. It is recommended to connect the DC coupled outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
MONO OUTPUT
The mono output, can be used as a line output, a headphone output or as a psuedo ground for capless driving of loads by SPKOUT. Recommended external components are shown below.
Figure 24 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1 = 1F: fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 will diminish the bass response. The function of R1 is to protect the line outputs from damage when used improperly.
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WM8974
The audio interface has four pins: * * * * ADCDAT: ADC data output DACDAT: DAC data input FRAME: Data alignment clock BCLK: Bit clock, for synchronisation
DIGITAL AUDIO INTERFACES
The clock signals BCLK, and FRAME can be outputs when the WM8974 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: * * * * Left justified Right justified IS DSP mode
2
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8974 audio interface may be configured as either master or slave. As a master interface device the WM8974 generates BCLK and FRAME and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8974 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 25 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
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Figure 26 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 27 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on the 2nd rising edge of BCLK (selectable by LRP) following a rising edge of FRAME. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. FRAMEP should be set to 0 in this mode.
Figure 28 DSP/PCM Mode Audio Interface
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REGISTER ADDRESS R4 Audio interface control 1 BIT LABEL ADCLRSWAP DEFAULT 0 DESCRIPTION Controls whether ADC data appears in `right' or `left' phases of FRAME clock: 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME Controls whether DAC data appears in `right' or `left' phases of FRAME clock: 0=DAC data appear in `left' phase of FRAME 1=DAC data appears in `right' phase of FRAME Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) Frame clock polarity 0=normal 1=inverted DSP Mode control 1 = Reserved 0 = Configures interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 8 BCP 0 BCLK polarity 0=normal 1=inverted
2
DACLRSWAP
0
4:3
FMT
10
6:5
WL
10
7
FRAMEP
0
Table 47 Audio Interface Control Audio Interface Control The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
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REGISTER ADDRESS R6 0 Clock generation control BIT MS LABEL DEFAULT 0
Production Data
DESCRIPTION Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8974 (MASTER) Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output
4:2
BCLKDIV
000
7:5
MCLKDIV
010
8
CLKSEL
1
Table 48 Clock Control Note that the setting MCLKDIV=000 and BCLKDIV=000 must not be used simultaneously.
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8974 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.
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REGISTER ADDRESS R5 Companding control BIT 0 LABEL LOOPBACK DEFAULT 0 DESCRIPTION Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. ADC companding 00=off 01=reserved 10=-law 11=A-law DAC companding 00=off 01=reserved 10=-law 11=A-law
2:1
ADC_COMP
0
4:3
DAC_COMP
0
Table 49 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x 1/A } for 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
BIT7 SIGN EXPONENT
BIT[6:4] MANTISSA
BIT[3:0]
Table 50 8-bit Companded Word Composition
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u-law Companding
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1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 29 u-Law Companding
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 30 A-Law Companding
AUDIO SAMPLE RATES
The WM8974 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately.
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REGISTER ADDRESS BIT SR LABEL DEFAULT 000 DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved
R7 3:1 Additional control
Table 51 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8974 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8974 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from an existing audio master clock. Figure 31 shows the PLL and internal clocking arrangment on the WM8974. The PLL can be enabled or disabled by the PLLEN register bit. Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
REGISTER ADDRESS R1 Power management 1 5
BIT
LABEL PLLEN
DEFAULT 0 PLL enable 0=PLL off 1=PLL on
DESCRIPTION
Table 52 PLLEN Control Bit
Figure 31 PLL and Clock Select Circuit
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PLLN = int R PLLK = int (224 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz.
Production Data The PLL frequency ratio R = f2/f1 (see Figure 31) can be set using the register bits PLLK and PLLN:
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 - 8)) = 3221225 = 3126E9h REGISTER ADDRESS R36 PLL N value 4 3:0 BIT LABEL PLLPRESCALE PLLN DEFAULT 0 1000 DESCRIPTION 0 = MCLK input not divided (default) 1= Divide MCLK by 2 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3
5:0 8:0 8:0
PLLK [23:18] PLLK [17:9] PLLK [8:0]
0Ch 093h 0E9h
Table 53 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 54. MCLK (MHz) (F1) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHz) 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 F2 (MHz) 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 PRESCALE POSTSCALE DIVIDE DIVIDE 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 R N (Hex) 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7 K (Hex) 86C220 3126E8 F28BD4 8FD525 45A1CA D3A06E 6872AF 3D70A3 2DB492 FD809F 1F76F7 EE009E 86C226 3126E8 F28BD4 8FD525 BOAC93 482296
7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778
Table 54 PLL Frequency Examples
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The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL register bits. The GPIO is only available in 2 wire mode. Note that SLOWCLKEN must be enabled when using the jack detect function. REGISTER ADDRESS R8 GPIO control BIT 2:0 LABEL GPIOSEL DEFAULT 000 DESCRIPTION CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved GPIO Polarity invert 0=Non inverted 1=Inverted PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4
GENERAL PURPOSE INPUT/OUTPUT
3
GPIOPOL
0
5:4
OPCLKDIV
00
Table 55 CSB/GPIO Control
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 56. The WM8974 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. MODE Low High INTERFACE FORMAT 2 wire 3 wire
Table 56 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits.
Figure 32 3-Wire Serial Control Interface
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2-WIRE SERIAL CONTROL MODE
Production Data
The WM8974 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8974). The WM8974 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8974, then the WM8974 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8974 returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8974 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8974 register address plus the first bit of register data). The WM8974 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8974 acknowledges again by pulling SDIN low. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8974 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
DEVICE ADDRESS (7 BITS)
RD / WR BIT
ACK (LOW)
CONTROL BYTE 1 (BITS 15 TO 8)
ACK (LOW)
CONTROL BYTE 1 (BITS 7 TO 0)
ACK (LOW)
SCLK START STOP
register address and 1st register data bit
remaining 8 bits of register data
Figure 33 2-Wire Serial Control Interface In 2-wire mode the WM8974 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8974 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.
POWER SUPPLIES
The WM8974 can use up to four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A large AVDD slightly improves audio quality. SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output drivers. SPKVDD can range from 2.5V to 5.5V. SPKVDD can be tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than AVDD (or 1.5 x AVDD for BOOST mode), the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD Can range from 1.71V to 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths.
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Production Data Note: * * DCVDD should be greater than or equal to 1.9V when using the PLL. DCVDD is less than or equal to DBVDD
WM8974
RECOMMENDED POWER UP/DOWN SEQENCE
In order to minimise output pop and click noise, it is recommended that the WM8974 device is powered up and down using one of the following sequences: Power Up When NOT Using the Output 1.5x Boost Stage: 1. 2. 3. 4. 5. 6. Turn on external power supplies. Wait for supply voltage to settle. Set BIASEN = 1, BUFIOEN = 1 and also the VMIDSEL[1:0] bits in the Power Management 1 register. * Notes 1 and 2. Wait for the VMID supply to settle. * Note 2. Enable DAC by setting DACEN = 1. Enable mixers as required. Enable output stages as required.
Power Up When Using the Output 1.5x Boost Stage: 1. 2. 3. 4. 5. 6. 7. Turn on external power supplies. Wait for supply voltage to settle. Enable 1.5x output boost. Set MONOBOOST = 1 and SPKBOOST = 1 as required. Set BIASEN = 1, BUFIOEN = 1, BUFDCOPEN = 1 and also the VMIDSEL[1:0] bits in the Power Management 1 register. * Notes 1 and 2. Wait for the VMID supply to settle. * Note 2. Enable DAC by setting DACEN = 1. Enable mixers as required. Enable output stages as required.
Power Down (all cases): 1. 2. 3. 4. Soft mute DAC by setting DACMU = 1. Disable power management register 1 by setting R1[8:0]=0x00. Disable all other output stages. Turn off external power supplies.
Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID (NOT using output 1.5x boost) or 1.5 x (AVDD/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2). Choose the value of the VMIDSEL bits based on the startup time (VMIDSEL=10 for slowest startup, VMIDSEL=11 for fastest startup). Startup time is defined by the value of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on VMID.
2.
In addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the PGAs to avoid any audible pops or clicks. PD Rev 4.2 March 2007 59
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WM8974
Production Data
Vpor_on Vpora
Power Supply
DGND
Vpor_off
POR
No Power POR Undefined POR
Device Ready Internal POR active DNC
I2S Clocks
DNC
ADC Internal State
tadcint
Power down Init Normal Operation PD Init
tadcint
Normal Operation Power down
tmidrail_on
(Note 1)
tmidrail_off
(Note 2)
Analogue Inputs ADCDAT pin
(Note 3)
AVDD/2 GD GD GD GD
ADCEN bit INPPGAEN bit VMIDSEL/ BIASEN bits
(Note 4)
ADC enabled
ADC off
ADC enabled
INPPGA enabled
VMID enabled
Figure 34 ADC Power Up and Down Sequence (not to scale)
SYMBOL tmidrail_on tmidrail_off tadcint
MIN
TYPICAL 500 >10 2/fs
MAX
UNIT ms s n/fs
Table 57 Typical POR Operation (typical values, not tested)
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Production Data Notes: 1.
WM8974
The analogue input pin charge time, tmidrail_on, is determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The analogue input pin discharge time, tmidrail_off, is determined by the analogue input coupling capacitor discharge time. The time, tmidrail_off, is measured using a 1F capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. While the ADC is enabled there will be LSB data bit activity on the ADCDAT pin due to system noise but no significant digital output will be present. The VMIDSEL and BIASEN bits must be set to enable analogue input midrail voltage and for normal ADC operation. ADCDAT data output delay from power up - with power supplies starting from 0V - is determined primarily by the VMID charge time. ADC initialisation and power management bits may be set immediately after POR is released; VMID charge time will be significantly longer and will dictate when the device is stabilised for analogue input. ADCDAT data output delay at power up from device standby (power supplies already applied) is determined by ADC initialisation time, 2/fs.
2.
3. 4. 5.
6.
Figure 35 DAC Power Up and Down Sequence (not to scale)
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WM8974
SYMBOL tline_midrail_on tline_midrail_off thp_midrail_on thp__midrail_off tdacint MIN TYPICAL 500 1 500 6 2/fs MAX UNIT ms s ms s n/fs
Production Data
Table 58 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time, tline_midrail_on, is mainly determined by the VMID pin charge time. This time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7F capacitor. It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. The same is also true if the DACDAT is removed at a non-zero value, and no mute function has been applied to the signal beforehand. The lineout discharge time, tline_midrail_off, is dependent upon the value of the lineout coupling capacitor and the leakage resistance path to ground. The values above were measured using a 10F output capacitor. The headphone charge time, thp_midrail_on, is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. The values above were measured using a 4.7F VMID decoupling capacitor. The headphone discharge time, thp_midrail_off, is dependent upon the value of the headphone coupling capacitor and the leakage resistance path to ground. The values above were measured using a 100F capacitor. The VMIDSEL and BIASEN bits must be set to enable analogue output midrail voltage and for normal DAC operation.
2.
3.
4.
5.
6.
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Production Data
WM8974
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS R10 DAC control R14 ADC control 3 BIT LABEL DACOSR128 0 DEFAULT DESCRIPTION DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR)
POWER MANAGEMENT
3
ADCOSR128
0
Table 59 ADC and DAC Oversampling Rate Selection
VMID
The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS R1 Power management 1 BIT 1:0 LABEL VMIDSEL DEFAULT 00 DESCRIPTION Reference string impedance to VMID pin (detemines startup time): 00=off (open circuit) 01=75k 10=300k 11=2.5k (for fastest startup)
Table 60 VMID Impedance Control
BIASEN
REGISTER ADDRESS R1 Power management 1 3 BIT LABEL BIASEN DEFAULT 0 DESCRIPTION Analogue amplifier bias control 0=Disabled 1=Enabled
Table 61 BIASEN Control
ESTIMATED SUPPLY CURRENTS
When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from DCVDD when DCVDD=1.8V and fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD.
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WM8974
Production Data
Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT BUFDCOPEN MONOEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL BOOSTEN INPPGAEN ADCEN MONOEN SPKPEN SPKNEN MONOMIXEN SPKMIXEN DACEN 0.1 0.2 1.4 (with clocks applied) 0.5 0.3 0.1 10K=>0.3, less than 0.1 for 100k/500k 0.2 0.2 x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9 0.2 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 0.2 0.2 x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9 AVDD CURRENT (MILLIAMPS)
Table 62 AVDD Supply Current
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Production Data
WM8974
REGISTER MAP
ADDR B[15:9]
DEC HEX
REGISTER NAME Software Reset Power manage't 1 Power manage't 2 Power manage't 3 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl GPIO DAC Control DAC digital Vol ADC Control ADC Digital Vol EQ1 - low shelf EQ2 - peak 1 EQ3 - peak 2 EQ4 - peak 3 EQ5 - high shelf DAC Limiter 1 DAC Limiter 2 Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3 Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 Attenuation ctrl Input ctrl INP PGA gain ctrl ADC Boost ctrl Output ctrl SPK mixer ctrl
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEF'T VAL (HEX)
0 1 2 3 4 5 6 7 8 10 11 14 15 18 19 20 21 22 24 25 27 28 29 30 32 33 34 35 36 37 38 39 40 44 45 47 49 50
00 01 02 03 04 05 06 07 08 0A 0B 0E 0F 12 13 14 15 16 18 19 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 2C 2D 2F 31 32
Software reset BUFDCOP EN 0 0 BCP 0 CLKSEL 0 0 0 0 HPFEN 0 EQMODE EQ2BW EQ3BW EQ4BW 0 LIMEN 0 NFU NFU NFU NFU ALCSEL ALCZC ALCMODE 0 0 0 0 0 0 0 0 0 PLLK[17:9] PLLK[8:0] 0 MBVSEL 0 PGABOOST 0 0 0 0 INPPGAZC 0 0 0 0 0 0 0 INPPGA MUTE MICP2BOOSTVOL 0 AUX2SPK 0 0 0 0 0 0 0 AUXMODE MONOATT SPKATTN N AUX2 INPPGA MICN2 INPPGA 0 MICP2 INPPGA 0 NFEN 0 0 0 0 0 ALCHLD ALCDCY 0 0 0 PLLPRE SCALE PLLK[23:18] NGEN ALCMAX 0 0 0 0 0 EQ1C EQ2C EQ3C EQ4C EQ5C LIMDCY LIMLVL NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] ALCMIN ALCLVL ALCATK NGTH PLLN[3:0] HPFAPP HPFCUT 0 0 0 0 0 MONOEN FRAMEP 0 0 MCLKDIV 0 0 DACMU 0 OPCLKDIV DEEMPH 0 GPIOPOL DACOSR 128 DACVOL ADCOSR 128 ADCVOL EQ1G EQ2G EQ3G EQ4G EQ5G LIMATK LIMBOOST 0 0 ADCPOL AMUTE AUXEN 0 SPKNEN WL 0 PLLEN 0 SPKPEN MICBEN BOOSTEN 0 FMT DAC_COMP BCLKDIV SR GPIOSEL 0 DACPOL BIASEN 0 MONO MIXEN BUFIOEN INPPGAEN SPK MIXEN 0 0 VMIDSEL ADCEN DACEN 0 000 000 000 050
DACLRSW ADCLRSW AP AP ADC_COMP 0
LOOPBACK 000 MS 140 SLOWCLKE 000 N 000 000 0FF 100 0FF 12C 02C 02C 02C 02C 032 000 000 000 000 000 038 00B 032 000 008 00C 093 0E9 000 003 010
INPPGAVOL 0 MONO BOOST 0 SPK BOOST 0 AUX2BOOSTVOL TSDEN BYP2SPK VROI DAC2SPK
000 002 000
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WM8974
ADDR B[15:9]
DEC HEX
Production Data REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF'T VAL (HEX) 039 BYP2 MONO DAC2 MONO 000
54 56
36 38
SPK volume ctrl MONO mixer ctrl
0 0
SPKZC 0
SPKMUTE MONO MUTE 0 0 0
SPKVOL AUX2 MONO
REGISTER BITS BY ADDRESS
Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS 0 (00h) 1 (01h) 8 BIT [8:0] LABEL RESET BUFDCOPEN DEFAULT N/A 0 Software reset Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) Reserved Auxilliary input buffer enable 0 = OFF 1 = ON PLL enable 0=PLL off 1=PLL on Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Analogue amplifier bias control 0=Disabled 1=Enabled Unused input/output tie off buffer enable 0=Disabled 1=Enabled Reference string impedance to VMID pin: 00=off (open circuit) 01=75k 10=300k 11=2.5k Reserved Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Reserved Input microphone PGA enable 0 = disabled 1 = enabled Reserved ADC Enable Control 0 = ADC disabled 1 = ADC enabled Reserved Analogue to Digital Converter (ADC) Input Signal Path Input Boost Auxiliary Inputs DESCRIPTION REFER TO Resetting the Chip Analogue Outputs
7 6 AUXEN
0 0
5
PLLEN
0
Master Clock and Phase Locked Loop (PLL) Microphone Biasing Circuit Power Management Enabling the Outputs Power Management
4
MICBEN
0
3
BIASEN
0
2
BUFIOEN
0
1:0
VMIDSEL
00
2 (02h)
8:5 4 BOOSTEN
0000 0
3 2 INPPGAEN
0 0
1 0 ADCEN
0 0
3 (03h)
8
0
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Production Data REGISTER ADDRESS 7 BIT LABEL MONOEN DEFAULT 0 MONOOUT enable 0 = disabled 1 = enabled SPKOUTN enable 0 = disabled 1 = enabled SPKOUTP enable 0 = disabled 1 = enabled Reserved Mono Mixer Enable 0 = disabled 1 = enabled Speaker Mixer Enable 0 = disabled 1 = enabled Reserved DAC enable 0 = DAC disabled 1 = DAC enabled BCLK polarity 0=normal 1=inverted Frame clock polarity 0=normal 1=inverted DSP Mode control 1 = Reserved 0 = Configures the interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode DESCRIPTION
WM8974
REFER TO Analogue Outputs
6
SPKNEN
0
Analogue Outputs
5
SPKPEN
0
Analogue Outputs
4 3 MONOMIXEN
0 0
Analogue Outputs
2
SPKMIXEN
0
Analogue Outputs
1 0 DACEN
0 0
Analogue Outputs
4 (04h)
8
BCP
0
Digital Audio Interfaces Digital Audio Interfaces
7
FRAMEP
0
Digital Audio Interfaces
4:3
FMT
10
Digital Audio Interfaces
2
DACLRSWAP
0
Controls whether DAC data appears in `right' or `left' phases of Digital Audio FRAME clock: Interfaces 0=DAC data appear in `left' phase of FRAME 1=DAC data appears in `right' phase of FRAME Controls whether ADC data appears in `right' or `left' phases of Digital Audio FRAME clock: Interfaces 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME Reserved Reserved DAC companding 00=off 01=reserved 10=-law 11=A-law Digital Audio Interfaces
1
ADCLRSWAP
0
0 5 (05h) 8:5 4:3 DAC_COMP
0 0000 00
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WM8974
REGISTER ADDRESS BIT 2:1 LABEL ADC_COMP DEFAULT 00 ADC companding 00=off 01=reserved 10=-law 11=A-law Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8974 (MASTER) Reserved Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Reserved Reserved PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 DESCRIPTION
Production Data REFER TO Digital Audio Interfaces
0
LOOPBACK
0
Digital Audio Interfaces
6 (06h)
8
CLKSEL
1
Digital Audio Interfaces Digital Audio Interfaces
7:5
MCLKDIV
010
4:2
BCLKDIV
000
Digital Audio Interfaces
1 0 MS
0 0
Digital Audio Interfaces
7 (07h)
8:4 3:1 SR
00000 000
Audio Sample Rates
0 8 (08h) 8:6 5:4 OPCLKDIV
0 000 00
General Purpose Input Output
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Production Data REGISTER ADDRESS 3 BIT LABEL GPIOPOL DEFAULT 0 GPIO Polarity invert 0=Non inverted 1=Inverted CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved Reserved 00 DACMU 0 Reserved DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled Reserved DAC Polarity Invert 0 = No inversion 1 = DAC output inverted Reserved DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Reserved HPFEN 1 High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 11 for details. ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Reserved DESCRIPTION
WM8974
REFER TO General Purpose Input Output General Purpose Input Output
2:0
GPIOSEL
000
9 (09h) 10 (0Ah)
8:0 8:7 6
Output Signal Path
5:4
DEEMPH
00
Output Signal Path
3
DACOSR128
0
Power Management Output Signal Path
2
AMUTE
0
1 0 DACPOL
0 0
Output Signal Path
11 (0Bh)
8 7:0 DACVOL
0 11111111
Output Signal Path
12 (0Ch) 13 (0Dh) 14 (0Eh)
8:0 8:0 8
Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management
7
HPFAPP
0
6:4 3
HPFCUT ADCOSR128
000 0
2:1
00
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WM8974
REGISTER ADDRESS 0 BIT LABEL ADCPOL DEFAULT 0 ADC Polarity 0=normal 1=inverted Reserved ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Reserved EQMODE 1 0 EQ1C 01 0 = Equaliser applied to ADC path 1 = Equaliser applied to DAC path Reserved EQ Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz 4:0 19 (13h) 8 EQ1G EQ2BW 01100 0 EQ Band 1 Gain Control. See Table 35 for details. Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz 11=500Hz 4:0 20 (14h) 8 EQ2G EQ3BW 01100 0 Band 2 Gain Control. See Table 35 for details. Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz 4:0 21 (15h) 8 EQ3G EQ4BW 01100 0 Band 3 Gain Control. See Table 35 for details. Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz 4:0 22 (16h) 8:7 EQ4G 01100 00 Band 4 Gain Control. See Table 35 for details. Reserved DESCRIPTION
Production Data REFER TO Analogue to Digital Converter (ADC)
15 (0Fh)
8 7:0 ADCVOL
0 11111111
Analogue to Digital Converter (ADC)
16 (10h) 17 (11h) 18 (12h)
8:0 8:0 8 7 6:5
Output Signal Path
Output Signal Path
Output Signal Path Output Signal Path
7 6:5 EQ2C
0 01
Output Signal Path
Output Signal Path Output Signal Path
7 6:5 EQ3C
0 01
Output Signal Path
Output Signal Path Output Signal Path
7 6:5 EQ4C
0 01
Output Signal Path
Output Signal Path
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Production Data REGISTER ADDRESS BIT 6:5 LABEL EQ5C DEFAULT 01 DESCRIPTION Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz 4:0 24 (18h) 8 EQ5G LIMEN 01100 0 Band 5 Gain Control. See Table 35 for details. Enable the DAC digital limiter: 0=disabled 1=enabled DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s 3:0 LIMATK 0010 DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 25 (19h) 8:7 6:4 LIMLVL 00 000 Reserved DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB
WM8974
REFER TO Output Signal Path
Output Signal Path Output Signal Path
7:4
LIMDCY
0011
Output Signal Path
Output Signal Path
Output Signal Path
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WM8974
REGISTER ADDRESS BIT 3:0 LABEL LIMBOOST DEFAULT 0000 DESCRIPTION DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB ... (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved 27 (1Bh) 8 7 NFU NFEN 0 0
Production Data REFER TO Output Signal Path
Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Notch filter enable: 0=Disabled 1=Enabled Notch Filter a0 coefficient, bits [13:7] Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC)
6:0 28 (1Ch) 8 7 6:0 29 (1Dh) 8 7 6:0 30 (1Eh) 8 7 6:0 32 (20h) 8
NFA0[13:7] NFU
0000000 0 0
Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Reserved Notch Filter a0 coefficient, bits [6:0] Analogue to Digital Converter (ADC)
NFA0[6:0] NFU
0000000 0 0
Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Reserved Notch Filter a1 coefficient, bits [13:7] Analogue to Digital Converter (ADC)
NFA1[13:7] NFU
0000000 0 0
Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Reserved Notch Filter a1 coefficient, bits [6:0] ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain) Reserved Set Maximum Gain of PGA when using ALC: 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Set minimum gain of PGA when using ALC: 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB Analogue to Digital Converter (ADC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC)
NFA1[6:0] ALCSEL
0000000 0
7:6 5:3 ALCMAX 111
2:0
ALCMIN
000
Input Limiter / Automatic Level Control (ALC)
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Production Data REGISTER ADDRESS 33 (21h) 8 BIT LABEL ALCZC DEFAULT 0 DESCRIPTION ALC zero cross detection. 0 = disabled 1 = enabled ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS ... (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode. Decay (gain ramp-up) time (ALCMODE =0) Per step 0000 0001 0010 1010 or higher 0011 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s
WM8974
REFER TO Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC)
7:4
ALCHLD
000
3:0
ALCLVL
1011
Input Limiter / Automatic Level Control (ALC)
34 (22h)
8
ALCMODE
0
Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC)
7:4
ALCDCY
0011
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE =1) Per step 0000 0001 0010 1010 90.8us 181.6us 363.2us 93ms Per 6dB 726.4us 1.453ms 2.905ms 744ms 90% of range 5.26ms 10.53ms 21.06ms 5.39s Input Limiter / Automatic Level Control (ALC)
... (time doubles with every step) 3:0 ALCATK 0010 ALC attack (gain ramp-down) time (ALCMODE = 0) Per step 0000 0001 0010 1010 or higher 0010 104us 208us 416us 106ms Per 6dB 832us 1.664ms 3.328ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE = 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s Input Limiter / Automatic Level Control (ALC) PD Rev 4.2 March 2007 73
... (time doubles with every step) 35 (23h) 8:4 3 NGEN 00000 0 Reserved ALC Noise gate function enable 1 = enable 0 = disable
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WM8974
REGISTER ADDRESS BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db ... (6dB steps) 111=-81dB Reserved 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Reserved Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Reserved Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB Reserved Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Reserved Auxiliary Input Mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Reserved Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write.
Production Data REFER TO Input Limiter / Automatic Level Control (ALC)
36 (24h)
8:5 4 PLLPRESCALE
0000 0
Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Analogue Outputs
3:0
PLLN[3:0]
1000
37 (25h)
8:6 5:0 PLLK[23:18]
000 001100
38 (26h)
8:0
PLLK[17:9]
010010011
39 (27h)
8:0
PLLK[8:0]
011101001
40 (28h)
8:3 2 MONOATTN
000000 0
1
SPKATTN
0
Analogue Outputs
0 44 (2Ch) 8 MBVSEL
0 0
Input Signal Path
7:4 3 AUXMODE
0000 0
Input Signal Path
2
AUX2INPPGA
0
Input Signal Path
1
MICN2INPPGA
1
Input Signal Path
0
MICP2INPPGA
1
Input Signal Path
45 (2Dh)
8 7 INPPGAZC
0 0
Input Signal Path
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Production Data REGISTER ADDRESS 6 BIT LABEL INPPGAMUTE DEFAULT 0 DESCRIPTION Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB
WM8974
REFER TO Input Signal Path
5:0
INPPGAVOL
010000
Input Signal Path
47 (2Fh)
8
PGABOOST
0
Input Boost Input Signal Path 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Controls the auxilliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Reserved Mono output boost stage control (see Table 37 for details) 0=No boost (output is inverting buffer) 1=1.5x gain boost Speaker output boost stage control (see Table 37 for details) 0=No boost (outputs are inverting buffers) 1 = 1.5x gain boost Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k Reserved Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Reserved Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of DAC to speaker mixer input 0 = not selected 1 = selected Analogue Outputs Analogue Outputs Analogue Outputs Input Signal Path Input Signal Path
7 6:4
0 MICP2BOOSTVOL 000
3 2:0
0 AUX2BOOSTVOL 000
49 (31h)
8:4 3 MONOBOOST
00000 0
2
SPKBOOST
0
Analogue Outputs
1
TSDEN
1
Output Switch
0
VROI
0
Analogue Outputs
50 (32h)
8:6 5 AUX2SPK
000 0
4:2 1 BYP2SPK
000 0
0
DAC2SPK
0
Analogue Outputs
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WM8974
REGISTER ADDRESS 54 (36h) 8 7 SPKZC 0 Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB ... (1.0 dB steps) 111001=0dB ... 000000=-57dB Reserved MONOOUT Mute Control 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Reserved Output of Auxilliary amplifier to mono mixer input: 0 = not selected 1 = selected BIT LABEL DEFAULT DESCRIPTION
Production Data REFER TO
Analogue Outputs
6
SPKMUTE
0
Analogue Outputs
5:0
SPKVOL
111001
Analogue Outputs
56 (38h)
8:7 6 MONOMUTE
0 0
Analogue Outputs
5:3 2 AUX2MONO
0 0
Analogue Outputs
1
BYP2MONO
0
Bypass path (output of input boost stage) to mono mixer input Analogue Outputs 0 = non selected 1 = selected Output of DAC to mono mixer input 0 = not selected 1 = selected Analogue Outputs
0
DAC2MONO
0
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Production Data
WM8974
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 63 Digital Filter Characteristics f > 0.546fs 0.546fs -80 29/fs dB +/- 0.035dB -6dB 0 0.5fs +/-0.035 dB 0.454fs 3.7 10.4 21.6 Hz f > 0.546fs 0.546fs -60 21/fs dB +/- 0.025dB -6dB 0 0.5fs +/- 0.025 dB 0.454fs TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. 3. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region Note that this delay applies only to the filters and does not include additional delays through other digital circuits. See Table 64 for the total delay. PARAMETER ADC Path Group Delay Total Delay (ADC analogue input to digital audio interface output) DAC Path Group Delay Total Delay (Audio interface input to DAC analogue output) Table 64 Total Group Delay Notes: 1. Wind noise filter is disabled. EQ disabled EQ enabled 34/fs 35/fs 36/fs 37/fs 38/fs 39/fs EQ disabled EQ enabled 26/fs 27/fs 28/fs 29/fs 30/fs 31/fs TEST CONDITIONS MIN TYP MAX UNIT
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WM8974
DAC FILTER RESPONSES
0.2
0 -20 Response (dB) -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
Production Data
0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 36 DAC Digital Filter Frequency Response
Figure 37 DAC Digital Filter Ripple
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
Response (dB)
0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2
-40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
0
0.1
0.2 Frequency (Fs)
0.3
0.4
0.5
Figure 38 ADC Digital Filter Frequency Response
Figure 39 ADC Digital Filter Ripple
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Production Data
WM8974
DE-EMPHASIS FILTER RESPONSES
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz)
0.30 0.25 0.20 Response (dB) 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz)
Figure 40 De-emphasis Frequency Response (32kHz)
Figure 41 De-emphasis Error (32kHz)
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 5000 10000 Frequency (Hz) 15000 20000
0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 5000 10000 Frequency (Hz) 15000 20000
Figure 42 De-emphasis Frequency Response (44.1kHz)
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 5000 10000 Frequency (Hz) 15000 20000
Response (dB)
Figure 43 De-emphasis Error (44.1kHz)
0.10 0.08 0.06 0.04 Response (dB) 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 5000 10000 Frequency (Hz) 15000 20000
Figure 44 De-emphasis Frequency Response (48kHz)
Figure 45 De-emphasis Error (48kHz)
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WM8974
HIGHPASS FILTER
Production Data
The WM8974 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cutoff of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cutoff frequency.
5 0 -5 -10 Response (dB)
10 0 -10 Response (dB)
0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
-15 -20 -25 -30 -35 -40
-20 -30 -40 -50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 46 ADC Highpass Filter Response, HPFAPP=0
Figure 47 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cutoff settings shown.
10 0 -10
Response (dB)
10 0 -10 -20 -30 -40 -50 -60
-20 Response (dB) -30 -40 -50 -60 -70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
-70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 48 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cutoff settings shown.
Figure 49 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cutoff settings shown.
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Production Data
WM8974
The WM8974 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
5-BAND EQUALISER
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
10
0
0
0
-5
-5
-10
-10
-15 -1 10
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 50 EQ Band 1 - Low Frequency Shelf Filter Cut-offs Figure 51 EQ Band 1 - Gains for Lowest Cut-off Frequency
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
10
0
0
0
-5
-5
-10
-10
-15 -1 10
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 52 EQ Band 2 - Peak Filter Centre Frequencies, EQ2BW=0
15
Figure 53 EQ Band 2 - Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 54 EQ Band 2 - EQ2BW=0, EQ2BW=1
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WM8974
Production Data
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 55 EQ Band 3 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 56 EQ Band 3 - Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 57
EQ Band 3 - EQ3BW=0, EQ3BW=1
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Production Data
WM8974
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 58 EQ Band 4 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 59 EQ Band 4 - Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 60
15
EQ Band 4 - EQ3BW=0, EQ3BW=1
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 61
EQ Band 5 - High Frequency Shelf Filter Cut-offsFigure 62
EQ Band 5 - Gains for Lowest Cut-off Frequency
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WM8974
Production Data Figure 63 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EQxBW=0 for the peak filters.
20
15
10
Magnitude (dB)
5
0
-5
-10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 63
Cumulative Frequency Boost/Cut
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Production Data
WM8974
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 64
Recommended External Components
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WM8974 PACKAGE DIAGRAM
FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DETAIL 1
D2 19 24 D
Production Data
DM045.A
18 EXPOSED GROUND 6 PADDLE
1 4 E2 INDEX AREA (D/2 X E/2) E
A
SEE DETAIL 2 13 12 e 6 2X 7 b 1 bbb M C A B 2X aaa C aaa C
TOP VIEW
BOTTOM VIEW
ccc C A3 A 0.08 C 5
DETAIL 1
DETAIL 2
45 degrees Datum
L 1 e R L1 Terminal tip e/2
C
SEATING PLANE
SIDE VIEW
A1
DETAIL 2
0.32mm EXPOSED GROUND PADDLE
W T A3 H b Exposed lead G
Half etch tie bar
DETAIL 2
Symbols A A1 A3 b D D2 E E2 e G H L L1 T W aaa bbb ccc REF: MIN 0.80 0 0.18 2.55 2.55
Dimensions (mm) NOM MAX NOTE 0.90 1.00 0.02 0.05 0.20 REF 1 0.25 0.30 4.00 2.70 4.00 2.70 0.50 BSC 0.213 0.1 0.40 0.1 0.2 2.80 2.80 2 2
0.30 0.03
0.50 0.15
7
Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VGGD-2.
NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-2. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT. 8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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PD Rev 4.2 March 2007 86
Production Data
WM8974
IMPORTANT NOTICE
Wolfson Microelectronics plc ("Wolfson") products and services are sold subject to Wolfson's terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson's products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer's own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party's products or services does not constitute Wolfson's approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson's standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person's own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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PD Rev 4.2 March 2007 87

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